Semiconductor device and manufacturing method thereof

ABSTRACT

A method for manufacturing a semiconductor device, includes providing a wiring substrate having a first surface and a second surface, the first surface being provided with a plurality of leads, after the providing of the wiring substrate, arranging a semiconductor chip with a main surface, a plurality of electrode pads formed at the main surface, and a back surface opposite to the main surface, over the first surface of the wiring substrate such that the back surface of the semiconductor chip is opposed to the first surface of the wiring substrate, after the arranging of the semiconductor chip, electrically coupling the electrode pads formed along three out of four sides of the main surface of the semiconductor chip to the leads disposed at the first surface of the wiring substrate via a plurality of metal wires, and after the electrically coupling of the electrode pads, forming a seal body over the first surface of the wiring substrate.

REFERENCE TO RELATED APPLICATION

This application is a Divisional Application of U.S. patent applicationSer. No. 14/328,527, which was filed on Jul. 10, 2014, and thedisclosure of which is incorporated herein in its entirety by referencethereto.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2013-150391 filed onJul. 19, 2013 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to semiconductor devices and manufacturingtechniques thereof, and more specifically, to a technique effectivelyapplied to a semiconductor device with a semiconductor chip mounted overa wiring substrate, and assembly of the semiconductor device.

Japanese Patent Publication No. 4942020 (Patent Document 1) discloses astacked structure including a laminate of two semiconductor chipsaccommodated in one package. Specifically, the two semiconductor chipsare stacked on each other over a module substrate, and respectivelycoupled to bonding leads on the module substrate via wires.

Further, Japanese Unexamined Patent Publication No. 2000-294684 (PatentDocument 2) discloses a structure including a semiconductor chip mountedat the center of a surface of a quadrilateral package base. A pluralityof bonding leads is arranged in two lines at the periphery of the centeron the same plane of the package base.

RELATED ART DOCUMENTS Patent Documents

[Patent Document 1]

Japanese Patent Publication No. 4942020

[Patent Document 2]

Japanese Unexamined Patent Publication No. 2000-294684

SUMMARY

For example, a for semiconductor devices mounted on electronic devices,such as a tablet mobile terminal, (hereinafter also referred to as a“package” or “semiconductor package”), when being mounted on a displayunit or the like of the electronic device, in most cases, thesemiconductor device is positioned on an elongated mounting substrateaccommodated at the margin of a main body of the display unit, such as aliquid crystal panel.

In such a case, the planar shape of a package substrate included in thesemiconductor device becomes elongated, which results in restrictions onplanar shape of the package substrate.

On the other hand, in order to improve the processing speed of thesemiconductor chip assembled in the semiconductor device, thesemiconductor chip including a combination of a memory circuit, such asa dynamic random access memory (DRAM), and a logic circuit, such as aprocessor is often used. Such a compound semiconductor chip preferablyhas a circuit layout with the memory circuit occupying a large area anda plurality of logic circuits disposed around the memory circuit so asto improve an area efficiency and a design efficiency.

Thus, a main surface of the compound semiconductor chip becomessubstantially square, which creates restrictions on planar shape of themain surface of the semiconductor chip.

That is to say, in the semiconductor device structure described above,the semiconductor chip having a substantially square shape is mounted onthe elongate package substrate. Further, the above-mentioned compoundsemiconductor chip includes the logic circuits in addition to the memorycircuit, leading to a relatively high number of pads for a probe testand wire bonding.

As a result, from the viewpoint of the space, it is difficult to arrangethe bonding wires at four sides of the semiconductor chip due to therelationship in planar shape between the package substrate andsemiconductor chip.

Although each of Patent Documents 1 and 2 discloses the structure withthe semiconductor chip and the substrate coupled together by bondingwires, these patent documents fail to take into consideration thestructure having the substantially square-shaped semiconductor chipmounted on the elongated substrate with many pads.

Other problems and new features of the present invention will beclarified in the following detailed description in connection with theaccompanying drawings.

According to one aspect of the invention, a semiconductor deviceincludes a wiring substrate having a plurality of bonding leads at anupper surface having a rectangular shape, a semiconductor chip mountedover the upper surface of the wiring substrate, and having a pluralityof electrode pads at a main surface having a rectangular shape, aplurality of metal wires for coupling the bonding leads of the wiringsubstrate to the electrode pads of the semiconductor chip, and aplurality of terminals for external coupling provided at a secondsurface of the wiring substrate. In the semiconductor device, the metalwires are arranged at three out of four sides of the main surface of thesemiconductor chip. Further, the bonding leads are provided in lines atthe first surface of the wiring substrate along a short side of thefirst surface outside the respective sides of any one of two pairs ofthe opposed sides of the main surface of the semiconductor chip, and themetal wires are electrically coupled to the leads.

According to the one embodiment of the invention, the semiconductordevice that complies with restrictions on layout on a mounting substrateside can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing one example of the structure of asemiconductor device according to one embodiment of the invention;

FIG. 2 is a side view showing the structure of the semiconductor devicein the longitudinal direction thereof shown in FIG. 1;

FIG. 3 is a backside view showing the backside structure of thesemiconductor device shown in FIG. 1;

FIG. 4 is a side view showing the structure of the semiconductor devicein the width direction thereof shown in FIG. 1;

FIG. 5 is a plan view showing the internal structure of thesemiconductor device shown in FIG. 1 seen through a seal body;

FIG. 6 is a cross-sectional view taken along the line A-A of FIG. 5;

FIG. 7 is a cross-sectional view taken along the line B-B of FIG. 5;

FIG. 8 is a plan view showing one example of a pad layout of asemiconductor chip mounted on the semiconductor device shown in FIG. 1;

FIG. 9 is a plan view showing one example of a layout of a circuit blockinside the semiconductor chip mounted on the semiconductor device shownin FIG. 1;

FIG. 10 is a plan view showing one example of the structure of an uppersurface of a wiring substrate to be used for assembly of thesemiconductor device shown in FIG. 1;

FIG. 11 is a plan view observed from the above of wiring patterns on thelower surface side of the wiring substrate shown in FIG. 10 by way ofexample;

FIG. 12 is a plan view showing one example of the structure obtainedafter die bonding in the assembly of the semiconductor device shown inFIG. 1;

FIG. 13 is a plan view showing one example of the structure obtainedafter wire bonding in the assembly of the semiconductor device shown inFIG. 1;

FIG. 14 is a plan view showing one example of a direction of chargingresin in a resin molding step in the assembly of the semiconductordevice shown in FIG. 1; and

FIG. 15 is a plan view showing one example of the state of the chargedresin in the resin molding step in the assembly of the semiconductordevice shown in FIG. 1.

DETAILED DESCRIPTION

In the following embodiments, the same or similar parts will not berepeatedly described in principle unless absolutely necessary.

The following preferred embodiments of the invention may be describedbelow by being divided into a plurality of sections or embodiments forconvenience, if necessary, which are not independent from each otherunless otherwise specified. One of the sections or embodiments may be amodified example, a detailed description, or supplementary explanationof a part or all of the other.

Even when referring to a specific number about an element and the like(including the number of elements, a numerical value, an amount, arange, and the like) in the following embodiments, the invention is notlimited to the specific number, and may take the number greater than, orless than the specific numeral number, unless otherwise specified, andexcept when limited to the specific number in principle.

The components (including elemental steps) in the embodiments below arenot necessarily essential unless otherwise specified, and except whenclearly considered to be essential in principle.

In the embodiments below, the term “composed of A”, “comprised of A”,“having A”, and “including A” as to the component and the like does notexclude elements other than the element “A”, unless otherwise specifiedand except when considered to be consisting of only the element A fromthe context. Likewise, when referring to the shape of one component, orthe positional relationship between the components in the followingembodiments, any shape or positional relationship substantially similaror approximate to that described herein may be included in the inventionunless otherwise specified and except when clearly considered not to beso in principle. The same goes for the above numerical value, and therange.

Preferred embodiments of the invention will be described in detail belowbased on the accompanying drawings. In all drawings for explaining theembodiments, parts having the same functions are indicated by the sameor similar reference characters, and the repeated description thereofwill be omitted. Even some plan views may be designated by hatching foreasy understanding.

PREFERRED EMBODIMENTS

FIG. 1 is a plan view showing one example of the structure of asemiconductor device according to this embodiment of the invention, FIG.2 is a side view showing the structure of the semiconductor device inthe longitudinal direction thereof shown in FIG. 1, FIG. 3 is a backsideview showing the backside structure of the semiconductor device shown inFIG. 1, and FIG. 4 is a side view showing the structure of thesemiconductor device in the width direction thereof shown in FIG. 1.FIG. 5 is a plan view showing the internal structure of thesemiconductor device shown in FIG. 1 seen through a seal body, FIG. 6 isa cross-sectional view taken along the line A-A of FIG. 5, and FIG. 7 isa cross-sectional view taken along the line B-B of FIG. 5. Further, FIG.8 is a plan view showing one example of a pad layout of a semiconductorchip mounted on the semiconductor device shown in FIG. 1, and FIG. 9 isa plan view showing one example of a layout of a circuit block insidethe semiconductor chip mounted on the semiconductor device shown in FIG.1.

The semiconductor device of this embodiment shown in FIGS. 1 to 7 is asemiconductor package in which a semiconductor chip is mounted over apackage substrate as a wiring substrate and electrically coupled to thepackage substrate by metal wires.

In this embodiment, the case where ball electrode disposed at the lowersurface of the wiring substrate serve as terminals for external couplingby way of the semiconductor device will be described. Thus, thesemiconductor device described in this embodiment is also a ball gridarray (BGA) type semiconductor package.

The semiconductor device of this embodiment has the semiconductor chipand the metal wires sealed with resin by resin mold.

The BGA5 structure as the semiconductor device of this embodiment willbe described below using FIGS. 1 to 7. The BGA5 is mounted on, forexample, a tablet personal computer or a mobile terminal device(electronic device), such as a cellular phone.

Thus, in many cases, when being mounted on a display unit or the like ofthe electronic device, the semiconductor device is mounted on anelongated mounting substrate accommodated at the margin of a main bodyof the display unit, such as a liquid crystal panel.

As shown in FIG. 1, the BGA 5 of this embodiment has its outerappearance with an elongated rectangular shape in the planar view so asto be mountable on an elongated narrow mounting substrate. That is, thewiring substrate (package substrate) 1 has an elongated rectangularshape in the planar view. A semiconductor chip 2 is mounted over anupper surface 1 a of the rectangular wiring substrate 1.

The wiring substrate 1 has the upper surface (first surface, frontsurface) 1 a, and a lower surface (second surface, back surface) 1 bopposite thereto. As shown in FIG. 5, a plurality of bonding leads(terminals, electrodes, leads, bonding stitch) 1 c is provided over theupper surface 1 a with the semiconductor chip 2 mounted thereover to beelectrically coupled to the semiconductor chip 2 via metal wires 4. Aplurality of wiring portions (wiring patterns) 1 e electrically coupledto the bonding leads 1 c is formed over the upper surface 1 a.

Each wiring portion 1 e extends outward or inward from each bonding lead1 c (toward a region under the chip, or a chip mounting region 1 h shownin FIG. 10), leading to a through hole wiring 1 g. As shown in FIG. 6,the wiring portion 1 e is electrically coupled to each land 1 d on thelower surface 1 b side via the through hole wiring 1 g.

As shown in FIG. 5, the upper surface 1 a of the wiring substrate 1 isformed in an elongated rectangular shape with a first side 1 aa and athird side 1 ac as a pair of opposed long sides, and a second side 1 aband a fourth side 1 ad intersecting the first and third sides 1 aa and 1ac as a pair of opposed short sides.

As shown in FIGS. 2 to 4, a plurality of solder balls (terminals forexternal coupling, external electrode terminals) 3 are arranged over thelower surface 1 b of the wiring substrate 1 in a grid pattern. As shownin FIGS. 6 and 7, the respective solder balls 3 are provided on aplurality of lands (terminals, electrodes, leads) 1 d disposed at thelower surface 1 b of the wiring substrate 1.

The bonding leads 1 c on the upper surface 1 a are electrically coupledto the lands 1 d on the lower surface 1 b via the wiring portions(wiring patterns) 1 e formed on the upper surface 1 a and the throughhole wirings 1 g or the like leading from the upper surface 1 a to thelower surface 1 b.

As shown in FIG. 5, the bonding leads 1 c formed at the upper surface 1a of the wiring substrate 1 are provided to be exposed at openings 1 fof an insulating film (solder resist film) on the upper surface 1 a.

The semiconductor chip 2 has a quadrilateral shape with a main surface(front surface) 2 a and a back surface 2 b opposite thereto. A pluralityof electrode pads (electrodes, terminals) 2 c are formed at the mainsurface 2 a. Specifically, the main surface 2 a is formed in asubstantially square planar shape with a first side 2 aa and a thirdside 2 ac as a pair of opposed long sides, and a second side 2 ab and afourth side 2 ad as a pair of opposed short sides intersecting the firstside 2 aa and the third side 2 ac, respectively. In this embodiment, thecase where the main surface 2 a of the semiconductor chip 2 issubstantially square will be described below.

As shown in FIG. 8, the electrode pads 2 c are provided along theperipheral edge (outer periphery) of the main surface 2 a of thesemiconductor chip 2.

As shown in FIGS. 6 and 7, the semiconductor chip 2 is bonded to thewiring substrate 1 via die bonding material (mounting material,adhesive) 6. That is, the back surface 2 b of the semiconductor chip 2is bonded to the upper surface 1 a of the wiring substrate 1 via the diebonding material 6. The die bonding material 6 is, for example, a resinadhesive or the like.

As shown in FIGS. 5 to 7, the bonding leads 1 c on the upper surface 1 aof the wiring substrate 1 are electrically coupled to the electrode pads2 c of the semiconductor chip 2 via the metal wires (conductive wires,conductive members) 4.

Thus, in the BGA 5, the respective electrode pads 2 c of thesemiconductor chip 2 are electrically coupled to the solder balls 3serving as the terminal for external coupling via the metal wire 4, thebonding leads 1 c of the wiring substrate 1, the wiring portions 1 e,and the through hole wirings 1 g, and the lands 1 d.

The metal wire 4 is formed, for example, of a gold wire, a copper wire,or the like.

As shown in FIGS. 2 and 4, the BGA 5 includes a seal body (resin member,resin portion) 7 formed of resin 9 (see FIG. 15) for sealing over theupper surface 1 a of the wiring substrate 1. The semiconductor chip 2and the metal wires 4 are sealed with resin by the seal body 7. The sealbody 7 is formed, for example, of thermosetting epoxy resin or the like.

As shown in FIG. 1, an index mark 7 a is formed on the surface of theseal body 7.

Now, the semiconductor chip 2 mounted over the BGA5 will be described.

As shown in FIG. 9, the semiconductor chip 2 of this embodiment is acomposite type with a memory circuit and a logic circuit. Specifically,the semiconductor chip 2 has a dynamic random access memory (DRAM,memory circuit) 2 e, and a plurality of logic circuits 2 f, 2 g, 2 h, 2i, and 2 j formed therein. That is, the semiconductor chip 2 is asemiconductor device including a combination of the plurality of logiccircuits and the DRAM 2 e within one chip.

Each of the logic circuits 2 f, 2 g, 2 h, 2 i, and 2 j is, for example,a processor, a frequency negative feedback circuit, and the like. Asshown in FIG. 9, the region of the DRAM 2 e in the chip has asubstantially square shape, and occupies most of the chip area withoutbeing divided into two or more regions. This is because the DRAM 2 e isformed to have one large shape similar to a square shape, which canimprove the area efficiency and design efficiency. In the surroundingsof the DRAM 2 e, the logic circuits 2 f, 2 g, 2 h, 2 i, and 2 j havingspecific functions (subjected to macro processing) and another logiccircuit 2 k (not subjected to macro processing) are formed, whereby theDRAM, the logic circuits, and the electrode pads 2 c are coupledtogether via metal wirings formed in the semiconductor chip.

As a result, the main surface 2 a of the semiconductor chip 2 has arectangular shape substantially similar to a square shape, with arelatively large area.

The semiconductor chip 2 is the composite one including a combination ofthe DRAM 2 e and the logic circuits 2 f, 2 g, 2 h, 2 i, 2 j and 2 k.Referring to FIG. 8, the electrode pads 2 c are formed at the peripheraledge of the rectangular main surface 2 a along the four respective sidesthereof. Thus, the semiconductor chip is a chip having a relativelylarge number of pads.

As mentioned above, the BGA 5 of this embodiment is provided on thecondition that the planar shape of the wiring substrate 1 is elongatedrectangular, and the planar shape of the semiconductor chip 2 to bemounted is similar to square (or rectangular). That is, the structuralconditions for the BGA 5 are limited by restrictions on shape of thewiring substrate 1, shape of the semiconductor chip 2, and the number ofelectrode pads of the semiconductor chip 2.

As shown in FIG. 5, in the BGA 5 of this embodiment, at the rectangularupper surface 1 a of the wiring substrate 1, a pair of opposed longsides of the main surface 2 a of the semiconductor chip 2 (first side 2aa, and third side 2 ac) are arranged along the long sides (first side 1aa, third side 1 ac) of the upper surface 1 a of the wiring substrate 1.At this time, the semiconductor chip 2 is arranged close to one end inthe width direction (direction along the short side) of the rectangularupper surface 1 a of the wiring substrate 1. In other words, one longside (first side 2 aa) of the semiconductor chip 2 is positioned closeto one long side (first side 1 aa) side of the wiring substrate 1.

The electrode pads 2 c are formed at the peripheral edges of fourrespective sides of the main surface 2 a of the semiconductor chip 2. Tothe electrode pads 2 c formed along three sides among the electrode pads2 c at the four sides, the metal wires (bonding wires) 4 can be coupled.

That is, in the BGA 5 of this embodiment, the first side 2 aa among thefour sides of the main surface 2 a of the semiconductor chip 2 isarranged close to the end of the wiring substrate 1 beside the firstside 1 aa of the wiring substrate 1, so that the wire bonding can beperformed on the three sides of the main surface 2 a of thesemiconductor chip 2. As a result, among the first side 2 aa and thethird side 2 ac as one pair of opposed long sides of the main surface 2a of the semiconductor chip 2, all the respective electrode pads 2 cformed at the peripheral edge along the first side 2 aa of the mainsurface 2 a cannot be coupled to the metal wire 4.

By making effective use of the longitudinal direction (the directionalong the first side 1 aa and the third side 1 ac as the long side) ofthe rectangular upper surface 1 a of the wiring substrate, the wirebonding is performed on both sides of the respective second side 2 aband fourth side 2 ad as a short side of the semiconductor chip 2 suchthat the loop height of the metal wires 4 is changed in stages. Thus,even the semiconductor chip 2 with relatively many pads can be coupledelectrically to the wiring substrate 1.

As mentioned above, the structure of the BGA 5 of this embodiment can beachieved by performing wire bonding on three sides of the semiconductorchip 2 so as to meet the above restrictions on shape of the wiringsubstrate 1 and the above restrictions on shape of the semiconductorchip 2 including the number of pads.

Here, the layout of the bonding leads (leads) 1 c formed on the uppersurface 1 a of the wiring substrate 1 will be described in detail.

As shown in FIG. 5, in the BGA 5, the bonding leads 1 c are arranged inlines in positions of the wiring substrate 1 outside the second andfourth sides 2 ab and 2 ad as the opposed short sides of thesemiconductor chip 2 in parallel to the second and fourth sides 1 ab and1 ad as the short sides of the upper surface 1 a. The bonding leads 1 care electrically coupled to a plurality of metal wires 4.

Thus, the metal wires 4 disposed along the long sides (first side 1 aaand third side 1 ac) of the upper surface 1 a of the wiring substrate 1are respectively arranged at two opposed sides (second side 2 ab andfourth side 2 ad) of the main surface 2 a of the semiconductor chip 2.Further, the metal wires 4 are also arranged at the third side 2 ac asthe long side of the main surface 2 a of the semiconductor chip 2.

That is, in the BGA 5, the metal wires 4 are arranged over therespective second side 2 ab (short side), third side 2 ac (long side),and fourth side 2 ad (short side) of the main surface 2 a of thesemiconductor chip 2. In other words, the metal wires 4 are arranged atthe second side 2 ab (short side), third side 2 ac (long side), andfourth side 2 ad (short side), respectively, to straddle each of thesides.

Specifically, the bonding leads 1 c are provided in lines outside thetwo respective opposed sides of the main surface 2 a of thesemiconductor chip 2 along the short sides (second side 1 ab, and fourthside 1 ad) of the upper surface 1 a. In the BGA 5 shown in FIG. 5, thebonding leads 1 c are provided in three lines along the second side 1 abof the wiring substrate 1 outside the second side 2 ab of thesemiconductor chip 2, and the bonding leads 1 c are provided in twolines along the fourth side 1 ad of the wiring substrate 1 outside thefourth side 2 ad of the semiconductor chip 2.

The metal wires 4 are coupled between the bonding leads 1 c and theelectrode pads 2 c of the semiconductor chip 2. As shown in FIG. 6, theloop height of the metal wire 4 coupled varies every line of the bondingleads 1 c.

That is, in either of the second and fourth sides 2 ab and 2 ad of themain surface 2 a of the semiconductor chip 2, as the line of the bondingleads 1 c along the short side (second side 1 ab and fourth side 1 ad)of the wiring substrate 1 is farther (spaced) away from thesemiconductor chip 2, the wire bonding is performed such that the loopheight of the metal wire 4 becomes higher.

Thus, in the BGA 5 shown in FIGS. 5 and 6, the metal wires 4 disposedbeside the second side 2 ab of the semiconductor chip 2 are arranged tohave three kinds (three stages) of loop heights because of the threelines of the bonding leads 1 c (bonding leads 1 ca, 1 cb, and 1 cc).

Specifically, on a side of the second side 2 ab of the semiconductorchip 2, the loop height of the first wire (metal wire 4) 4 a coupled tothe bonding lead 1 ca is lowest, the loop height of the third wire(metal wire 4) 4 c coupled to the bonding lead 1 cc is highest, and theloop height of the second wire (metal wire 4) 4 b coupled to the bondinglead 1 cb is an intermediate one.

On the other hand, the metal wires 4 disposed beside the fourth side 2ad of the semiconductor chip 2 are arranged to have two kinds (twostages) of loop heights because of the two lines of the bonding leads 1c (bonding leads 1 cd, and 1 ce).

Specifically, on a side of the fourth side 2 ad of the semiconductorchip 2, the loop height of the fifth wire (metal wire 4) 4 e coupled tothe bonding lead 1 ce is higher than that of the fourth wire (metal wire4) 4 d coupled to the bonding lead 1 cd.

Thus, the wire loops are formed in multiple stages (with a plurality ofloop heights), which can prevent the occurrence of electric shortcircuit between the metal wires respectively coupled to the lines of thebonding leads 1 c formed in lines.

In the semiconductor chip 2 as shown in FIG. 8, the electrode pads 2 cband 2 cd formed on the main surface 2 a along the two opposed shortsides (second side 2 ab and fourth side 2 ad) of the main surface 2 aare disposed in a staggered arrangement. By placing the electrode pads 2c in the staggered arrangement, the number of electrode pads at theedges of the short sides (second side 2 ab and fourth side 2 ad) of themain surface 2 a of the semiconductor chip 2 can be increased.

In bonding the metal wires 4 in the multiple stages, the staggeredarrangement can displace each pad position by half a pitch, therebypreventing the interference between the metal wires (electric shortcircuit).

As shown in FIG. 5, the metal wires 4 are arranged beside the third side2 ac as one long side intersecting the two opposed sides (second side 2ab and fourth side 2 ad as a short side) of the main surface 2 a of thesemiconductor chip 2. That is, the electrode pads 2 cc (2 c) aredisposed in one line along the peripheral edge of the third side 2 ac asone long side of the main surface 2 a of the semiconductor chip shown inFIG. 8. On the other hand, in response to the electrode pads 2 cc of thesemiconductor chip 2, the bonding leads 1 cf (1 c) are provided in oneline at the upper surface 1 a of the wiring substrate 1 along the thirdside 1 ac as the long side of the upper surface 1 a, outside one side(third side 2 ac) intersecting the two opposed short sides of thesemiconductor chip 2.

As shown in FIGS. 5 and 7, the electrode pads 2 cc (2 c) formed alongthe third side (long side) 2 ac of the main surface 2 a of thesemiconductor chip 2 are electrically coupled to the bonding leads 1 cfon the upper surface 1 a of the wiring substrate 1 positioned outsidethe third side 2 ac of the semiconductor chip 2 via a plurality of sixthwires (metal wires 4) 4 f.

As mentioned above, the bonding leads 1 c are laid out in one, two, andthree lines for respective sides of a chip mounting portion (chipmounting region 1 h shown in FIG. 10) at the upper surface 1 a of thewiring substrate 1, whereby the wire bonding is performed on the threesides (second side 2 ab, third side 2 ac, and fourth side 2 ad) of themain surface 2 a of the semiconductor chip 2 (three-sided bonding).

On a side of the third side 2 ac of the two opposed long sides of themain surface 2 a of the semiconductor chip 2 as a long side with themetal wires 4 formed thereon, the wiring portion 1 e as the wiringpattern is not formed outside the line of the bonding leads 1 cf (1 c)positioned beside the third side 2 ac of the semiconductor chip 2 at theupper surface 1 a of the wiring substrate 1 of the wiring portion 1 e.

That is, as shown in FIG. 10 to be described later, the bonding leads 1cf provided along the third side (long side) 1 ac of the wiringsubstrate 1 extend toward the inner region (chip mounting region 1 h)and not toward the outer region of the arrangement, and are electricallycoupled to the lower surface side lands 1 d shown in FIG. 11 via thethrough hole wirings 1 g in the inner region.

In the BGA 5, the electrode pads (first electrode pads) 2 ca(2 c) areformed at the main surface 2 a along the first side (long side) 2 aa nothaving the metal wires 4 disposed therein, among the sides of therectangular main surface 2 a of the semiconductor chip 2. Any one ofthese electrode pads 2 ca is not coupled to the metal wire 4. In otherwords, the three-sided bonding is performed, so that the metal wire 4 isnot coupled to the electrode pads 2 ca formed at the peripheral edge ofthe first side 2 aa of the main surface 2 a of the semiconductor chip 2.

The electrode pads 2 ca(2 c) to which the metal wire 4 at the first side2 aa of the semiconductor chip 2 is not coupled are electrically coupledto a protective circuit formed inside the semiconductor chip 2.

That is, each of the electrode pads 2 ca formed along the one side(first side 2 aa) not subjected to the wire bonding at the main surface2 a of the semiconductor chip 2 is a dummy electrode pad electricallycoupled to the protective circuit (power source) within the chip.

This can reduce electrostatic breakdown (or stabilize resistance toelectrostatic breakdown).

As mentioned above, in the BGA 5 of this embodiment, the semiconductorchip 2 having the substantially square planar shape is mounted over theelongated rectangular wiring substrate 1, the metal wires 4 are arrangedat three sides of the main surface 2 a of the semiconductor chip 2, andthe metal wires 4 respectively disposed at two short sides of thesemiconductor chip 2 are set to have different kinds of loop heights, sothat the three-sided bonding can be performed on the substantiallysquare semiconductor chip 2.

Thus, in the structure having the semiconductor chip 2 with asubstantially square planar shape mounted over the elongated rectangularwiring substrate 1, the three-sided bonding can be applied to mount thesemiconductor chip 2 with the substantially square shape over theelongated wiring substrate 1. Additionally, the semiconductor chip 2with many electrode pads can be mounted, which can achieve the BGA(semiconductor device) 5 with the above-mentioned structure.

That is, even the semiconductor device with restrictions on planar shapeof the wiring substrate 1, restrictions on planar shape of thesemiconductor chip 2, and restrictions on the number of the electrodepads 2 c can achieve the structure required.

In other words, even under the restrictions on layout on the mountingsubstrate side, such as a circuit substrate for mounting thesemiconductor device (BGA 5), this embodiment can achieve thesemiconductor device (BGA 5) that can be mounted over the mountingsubstrate while complying with restrictions on layout on the mountingsubstrate side.

Next, a manufacturing method of the BGA (semiconductor device) 5 of thisembodiment will be described.

FIG. 10 is a plan view showing one example of the structure of an uppersurface of a wiring substrate to be used for assembly of thesemiconductor device shown in FIG. 1, FIG. 11 is a perspective plan viewseen from the above of wiring patterns on the lower surface side of thewiring substrate shown in FIG. 10 by way of example, FIG. 12 is a planview showing one example of the structure obtained after die bonding inthe assembly of the semiconductor device shown in FIG. 1, and FIG. 13 isa plan view showing one example of the structure obtained after wirebonding in the assembly of the semiconductor device shown in FIG. 1.Further, FIG. 14 is a plan view showing one example of a direction ofcharging resin in a resin molding step in the assembly of thesemiconductor device shown in FIG. 1, and FIG. 15 is a plan view showingone example of the state of charged resin in the resin molding step inthe assembly of the semiconductor device shown in FIG. 1.

First, a multi-piece substrate 8 shown in FIG. 15 is provided. Themulti-piece substrate 8 has a plurality of device regions (packageregions, semiconductor device regions) 8 a in each of which the BGA 5can be formed, and which are partitioned off. In this embodiment, forsimplifying the description, the assembly of the BGA 5 will be describedbelow by taking only one device region 8 a (wiring substrate 1) as anexample.

First of all, as shown in FIGS. 10 and 11, the wiring substrate 1 isprovided which has the upper surface 1 a with a rectangular shape andthe lower surface 1 b opposite thereto. The bonding leads 1 c aredisposed in the surroundings of the three sides of the chip mountingregion 1 h on the upper surface 1 a.

The bonding leads 1 c formed around the chip mounting region 1 h on theupper surface 1 a of the wiring substrate 1 are respectively disposedalong the three sides of the quadrilateral chip mounting region 1 h. Thebonding leads 1 c are laid out in one line, two lines, and three linesfor the respective three sides of the chip mounting region 1 h.

The bonding leads 1 c are provided along the second side 1 ab in threelines (bonding leads 1 ca, 1 cb, and 1 cc) in a region between the chipmounting region 1 h and the second side (short side) 1 ab of the wiringsubstrate 1. On the other hand, the bonding leads 1 c are provided alongthe fourth side 1 ad in two lines (bonding leads 1 cd, and 1 ce) in aregion between the chip mounting region 1 h and the fourth side (shortside) 1 ad.

Further, the bonding leads 1 cf are provided along the third side 1 acin one line in a region between the chip mounting region 1 h and thethird side (long side) 1 ac.

As shown in FIG. 11, a plurality of lands 1 d are formed in parallel ina grid pattern on the lower surface side of the wiring substrate 1. Thebonding leads 1 c on the upper surface side are electrically coupled tothe lands 1 d on the lower surface side via the wiring portions 1 eformed on the upper surface 1 a and the lower surface 1 b, and thethrough hole wirings 1 g.

The shape of the appearance (planar shape) of the wiring substrate 1 ina planar view is elongated rectangular such that the BGA 5 is mountableon the elongated narrow mounting substrate.

Thereafter, die bonding is performed. At this time, the semiconductorchip 2 having the quadrilateral main surface 2 a, the pads 2 c formed atthe main surface 2 a, and the back surface 2 b opposite to the mainsurface 2 a are disposed over the upper surface 1 a of the wiringsubstrate 1 such that the back surface 2 b of the semiconductor chip 2is opposed to the upper surface 1 a of the wiring substrate 1.

As shown in FIG. 8, the electrode pads 2 c of the semiconductor chip 2are provided at the peripheral edges of the main surface 2 a along therespective four sides of the main surface 2 a. The electrode pads 2 cband 2 cd formed along a pair of opposed short sides of the main surface2 a, namely, second side 2 ab and fourth side 2 ad, among the electrodepads 2 c are disposed in a staggered arrangement.

The electrode pads 2 ca and 2 cc are respectively formed in one linealong a pair of opposed long sides of the main surface 2 a, namely, thefirst side 2 aa and third side 2 ac. The electrode pads (first electrodepads) 2 ca provided at the peripheral edge along the first side 2 aa asone long side are electrically coupled to the protective circuit withinthe chip. Thus, each of the electrode pads 2 ca is a dummy electrodepad.

As shown in FIG. 9, the semiconductor chip 2 is a composite type with amemory circuit and a logic circuit. Specifically, the semiconductor chip2 has the DRAM (memory circuit) 2 e, and a plurality of logic circuits 2f, 2 g, 2 h, 2 i, and 2 j, which are formed therein. That is, thesemiconductor chip 2 is a semiconductor device including a combinationof the plurality of logic circuits and the DRAM 2 e within one chip.

The region of the DRAM 2 e in the chip has a substantially square shape,and occupies most of the chip area without being divided into two ormore regions. This is because the DRAM 2 e is formed to have one largeshape similar to a square shape, which can improve the area efficiencyand design efficiency. As a result, the main surface 2 a of thesemiconductor chip 2 has a rectangular shape similar to a square shape,with a relatively large area.

The semiconductor chip 2 is the composite one including a combination ofthe DRAM 2 e and the logic circuits 2 f, 2 g, 2 h, 2 i, 2 j and 2 k.Referring to FIG. 8, the electrode pads 2 c are formed at the peripheryof the rectangular main surface 2 a along the four respective sidesthereof. Thus, the semiconductor chip is a chip having a relativelylarge number of pads.

The semiconductor chip 2 described above has the structure shown in FIG.12 which includes the chip mounting region 1 h on the upper surface 1 aof the wiring substrate 1 shown in FIG. 10. At this time, as shown inFIG. 6, the semiconductor chip 2 is mounted over the upper surface 1 aof the wiring substrate 1 via the die bonding material (adhesive) 6.

In the BGA 5 of this embodiment, the semiconductor chip 2 is disposedover the wiring substrate 1 such that the first side 2 aa and the thirdside 2 ac as a pair of long sides opposed to the main surface 2 a of thesemiconductor chip 2 extend along the first side 1 aa and the third side1 ac, respectively, as a pair of long sides opposed to the upper surface1 a of the wiring substrate 1.

That is, as shown in FIG. 12, the semiconductor chip 2 is mounted overthe wiring substrate 1 such that a pair of long sides (firs side 2 aa,third side 2 ac) of the semiconductor chip 2 extends along the opposedlong sides (first side 1 aa, third side 1 ac) of the wiring substrate 1.

Thus, the long side of the wiring substrate 1 and the long side of thesemiconductor chip 2 are arranged to extend along each other, and theshort side of the wiring substrate 1 and the short side of thesemiconductor chip 2 are also arranged to extend along each other.

Thereafter, wire bonding is performed. As shown in FIG. 13, theelectrode pads 2 c (2 cb, 2 cc, 2 cd) formed along three of the foursides of the main surface 2 a of the semiconductor chip 2, and thebonding leads 1 c at the upper surface 1 a of the wiring substrate 1 areelectrically coupled together via the metal wires 4.

At this time, as shown in FIG. 6, the metal wires 4 coupled to theelectrode pads 2 cb disposed along the second side 2 ab of the mainsurface 2 a of the semiconductor chip 2 are subjected to wire bonding insuch a manner as to have three different loop heights.

Specifically, the first wires 4 a coupled to the bonding leads 1 caprovided in the positions (line) closest to the semiconductor chip 2 areset to have the lowest loop height, while the third wires 4 c coupled tothe bonding leads 1 cc provided in the positions (line) farthest fromthe semiconductor chip 2 have the highest loop height in performing thewire bonding. Further, the second wires 4 b coupled to the bonding leads1 cb disposed in the intermediate line are set to have the intermediateloop height in performing the wire bonding.

On the other hand, the metal wires 4 coupled to the electrode pads 2 cdprovided along the fourth side 2 ad of the main surface 2 a of thesemiconductor chip 2 are set to have two different kinds of loop heightsin performing the wire bonding.

Specifically, the loop height of the fourth wire 4 d coupled to thebonding leads 1 cd provided in the positions (line) close to (inside)the semiconductor chip 2 among the bonding leads 1 c in two lines areset to be lower than that of the fifth wire 4 e coupled to the bondinglead 1 ce provided in the positions (line) far away from (outside) thesemiconductor chip 2 in performing the wire bonding.

That is, on a side of the fourth side 2 ad of the semiconductor chip 2,the loop height of the fifth wire (metal wire 4) 4 e is set higher thanthat of the fourth wire (metal wire) 4 d in performing the wire bonding.

In this way, the wire bonding is performed in such a manner that themetal wires 4 have a plurality of different kinds of loop height, whichcan prevent the occurrence of the electric short circuit between themetal wires formed by performing the wire bonding on the respectivebonding leads 1 c formed in the lines, such as two lines or three lines.

As shown in FIG. 7, the sixth wires (metal wires 4) 4 f coupled to thebonding leads 1 cf are provided in a region between the semiconductorchip 2 and the third side (long side) 1 ac of the wiring substrate 1,and are set to have one type of loop height in performing the wirebonding.

Note that the wire bonding is performed in the order of increasing theloop height in order to perform the wire bonding with a plurality ofkinds of (multiple stages) of loop heights.

In this way, the wire bonding on the three sides (second side 2 ab,third side 2 ac, and fourth sides 2 ad) of the main surface 2 a of thesemiconductor chip 2 is completed. Thus, the electrode pads (firstelectrode pads) 2 ca provided along the first side 2 aa are the dummyelectrode pads, where the wire bonding is not performed.

Then, resin molding is performed. As shown in FIGS. 6 and 7, thesemiconductor chip 2 and the metal wires 4 are sealed with resin,thereby forming the seal body 7 over the upper surface 1 a of the wiringsubstrate 1.

Referring to FIG. 14, in the resin molding step of this embodiment,resin 9 for sealing (resin) shown in FIG. 15 is charged from the thirdside 2 ac opposed to the first side 2 aa without any metal wires 4 amongfour sides of the main surfaces 2 a of the semiconductor chip 2, therebyproducing the seal body 7 as a single unit.

That is, when charing the resin in the resin molding step, the resin 9for sealing is charged in the resin charging direction P from the thirdside 2 ac opposed to the first side 2 aa not having the metal wires 4 atthe main surface 2 a of the semiconductor chip 2.

At this time, as shown in FIG. 15, the resin 9 for sealing flows to therespective device regions 8 a of the multi-piece substrate 8 in theflowing direction Q via a pot 10 and a runner 11.

In charging the resin, as the resin 9 for sealing is located fartheraway from the charging side (sealing inlet) S in each device region 8 a,the curing of the resin 9 is promoted, thereby easily inducing the wireflow. That is, in the portion R shown in FIG. 15, the wire flow of theresin 9 for sealing is more likely to be generated.

In the assembly of the BGA 5 of this embodiment, the wire bonding is notperformed on one of the four sides of the main surface 2 a of thesemiconductor chip 2 without disposing the metal wire 4 at this side.When charging the resin in the resin molding step, the resin 9 forsealing is charged from the third side 2 ac opposed to the first side 2aa not having any metal wires 4 of the semiconductor chip 2, toward thefirst side 2 aa side, so that the metal wire 4 is not arranged on theside T far away from the charging side S of the resin 9 for sealing,which hardly causes the wire flow.

That is, the metal wire 4 is not arranged on the side that promotes thecuring of the resin 9 for sealing, which can suppress the occurrence ofthe wire flow. In short, the resin 9 for sealing charged can reduceinconveniences, including the contact of the metal wire 4 with anotheradjacent metal wire 4 because of the wire flow.

In the way described above, the seal body 7 is formed as a single unitover the multi-piece substrate 8, thus resulting in completion of theresin mold step.

Then, as shown in FIG. 6, the solder balls (terminals for externalcoupling, external electrode terminal) 3 are formed over the respectivelands 1 d at the lower surface 1 b of the wiring substrate 1(multi-piece substrate 8).

Thereafter, the multi-piece substrate 8 shown in FIG. 15 is cut into apackage size, which completes the assembly of the BGA 5.

Although the invention made by the inventors has been specificallydescribed based on the embodiments, the invention is not limited to theabove embodiments. It is apparent that various modifications and changescan be made without departing from the scope of the invention.

Although this embodiment has explained that the main surface 2 a of thesemiconductor chip 2 is formed in a rectangular shape similar to asquare shape by way of example, the main surface 2 a of thesemiconductor chip 2 may be formed in a square shape.

Although in the above embodiments, the semiconductor device is the BGAby way of example, the semiconductor device may be a land grid array(LGA) including conductive members provided at the surfaces of the lands1 d on the lower surface 1 b of the wiring substrate 1.

What is claimed is:
 1. A method for manufacturing a semiconductordevice, comprising: providing a wiring substrate having a first surfaceand a second surface opposite thereto, the first surface being formed ina rectangular shape and provided with a plurality of leads; after theproviding of the wiring substrate, arranging a semiconductor chip with aquadrilateral main surface, a plurality of electrode pads formed at themain surface, and a back surface opposite to the main surface, over thefirst surface of the wiring substrate such that the back surface of thesemiconductor chip is opposed to the first surface of the wiringsubstrate; after the arranging of the semiconductor chip, electricallycoupling the electrode pads formed along three out of four sides of themain surface of the semiconductor chip to the leads disposed at thefirst surface of the wiring substrate via a plurality of metal wires;and after the electrically coupling of the electrode pads, forming aseal body over the first surface of the wiring substrate by sealing thesemiconductor chip and the metal wires with resin, wherein the formingof the seal body comprises charging a resin for sealing from one sideopposed to one of four sides of the main surface of the semiconductorchip not having the metal wires disposed thereat to thereby form theseal body.
 2. The method for manufacturing a semiconductor deviceaccording to claim 1, wherein the semiconductor chip includes a memorycircuit and a logic circuit.
 3. The method for manufacturing asemiconductor device according to claim 2, wherein the metal wiresdisposed in parallel along a short side of the first surface of thewiring substrate are arranged at two respective opposed sides of themain surface of the semiconductor chip, wherein the leads are providedin a plurality of lines along the short side of the first surfaceoutside the two respective opposed sides of the chip, and wherein themetal wires are electrically coupled to the leads.
 4. The method formanufacturing a semiconductor device according to claim 2, wherein themetal wires are arranged at one side intersecting the two opposed sidesof the main surface of the semiconductor chip, wherein the leads arearranged in one line outside the intersecting one side at the firstsurface of the wiring substrate, and wherein the metal wires areelectrically coupled to the leads.
 5. The method for manufacturing asemiconductor device according to claim 1, wherein the plurality ofleads are provided in: a plurality of lines at the first surface of thewiring substrate along a short side of the first surface outsiderespective sides of any one of two pairs of the opposed sides of themain surface of the semiconductor chip; and a line formed along a longside of the first surface, a distance between the short side of thefirst surface and the plurality of lines being greater than a distancebetween the long side of the first surface and the line formed along thelong side of the first surface, and wherein the metal wires areelectrically coupled to the leads.